NEXVOLT
NEXT FUTURE

未來從此刻開始

ABOUT US

ABOUT NEXVOLT
關於新伏

NEXVOLT stems from the founding team’s long-term, cross-disciplinary track record—spanning epitaxy, device design, process integration, packaging/thermals, and reliability. Since 2005–2013, we have focused on GaN material physics and AlGaN/GaN hetero-epitaxy, establishing core capabilities in stress/defect engineering (deep-level control of C/Fe/O, AlN spacer, superlattice/graded buffers), p-GaN E-mode gate reliability, D-mode optimized circuits (direct-drive / cascode with co-designed gate drive, and protection), dynamic RDS(on) suppression, and field-plate electric-field shaping—extended further to parasitics minimization and near-junction thermal paths at the package/module level. Building on this base, we position Ga₂O₃-in-GaN composite/hetero layers as a mid- to long-term performance amplifier, enabling a planned expansion from 650 V toward 1200 V+ and 2000 V-class platforms across both lateral (p-GaN E-mode / D-mode + cascode) and vertical (GaN-on-GaN) device architectures, with the objective of concurrently elevating critical breakdown field (Ecrit), dynamic stability, and thermal robustness.

Beyond products and IP licensing, NEXVOLT provides professional education consulting and technical solutions: curriculum/workshop design (GaN/Ga₂O₃, epitaxy-to-reliability full stack), in-house training and hands-on enablement, design reviews with yield/failure-mechanism diagnostics, and JEDEC/AEC-Q reliability implementation with documentation support. Centered on a GaN volume-production platform and Ga₂O₃ as a forward-looking enhancer, we deliver an end-to-end engineering pipeline—Epitaxy (MOCVD/MBE) → Design → Wafer Process → Packaging & Thermal → Reliability—to translate materials innovation, device performance, drive/protection co-design, and lifetime modeling into manufacturable, commercial solutions for fast charging, data-center/storage power, and automotive power electronics.

SCOPE of BUSINESS
營業項目

Power Devices (Products)

Scope: Mass production of 650 V lateral GaN HEMT; 900–1200 V in development (lateral and vertical in parallel); forward-looking >1200–2000 V vertical roadmap (GaN-on-GaN / engineered substrates, Ga₂O₃ as a long-term enhancer).
Key Technologies: p-GaN E-mode, D-mode + cascode optimized drive; multi-stage field-plate equalization; in-situ / ex-situ passivation; dynamic RDS,ON control; near-junction thermal paths and low-parasitic packaging (DFN/QFN, TOLL, half-bridge SiP).
Deliverables: Bare die / wafer / packaged devices, binned by RDS,ON, package, and reliability grade.

Patents & IP Licensing（Licensing）

Coverage: Epitaxial structures (AlN spacer, buffer/channel co-design), field-plate / gate engineering, package / SiP layouts, and reliability methodologies (JEDEC / AEC-Q).
Models: Territory- or application-specific licensing with tech-transfer documentation + reference flows.

Joint Development（NRE / JDM）

Process: Co-specification → engineering lots / pilot → reliability & third-party testing → mass-production ramp.
Deliverables: Engineering samples (650 V production platform, 1200 V development samples), EVB / reference designs, test & certification reports.
Co-Design: D-mode + cascode drive/protection co-design; package-parasitic equivalence and layout co-simulation.

Consulting & Education

Scope: Epitaxy → Reliability full-stack consulting, yield / failure-mechanism diagnostics, RDS,ON, dyn / Vth drift mitigation.
Education Services: Courses & workshops, in-house training, hands-on enablement; support to establish internal design / measurement / reliability workflows and KPIs.

OUR GOAL
里程碑

2005–2013

Device Platform Built

Formed the 650 V lateral GaN platform and process windows (selective etch, low-R_c ohmic, in-situ / ex-situ passivation), establishing a stable base for volume-grade designs.

2019–2024

Forward Expansion

Launch NEXVOLT with IP / Licensing / Consulting offerings; release 900–1200 V engineering samples (lateral & vertical); complete Ga₂O₃ Proof of Concept (POC)—a forward-looking enhancer, not a current mass product.

Research Foundations

Established expertise in AlGaN/GaN heteroepitaxy and stress/defect engineering; built key p-GaN E-mode / D-mode epitaxy and gate-stack know-how; reduced defect density via AlN spacer, superlattice/graded buffers, and deep-level control (treating foreign impurity elements as deep-level defects to be suppressed).

2014–2018

Mass Production & Methodology / System Integration

Achieved 650 V multi-bin mass production; implemented JEDEC reliability with failure-mechanism diagnostics; released SiP half-bridge prototypes and a co-designed gate-drive/protection methodology; completed fast-charger demos, driving parasitics minimization and near-junction thermal paths at module level for improved high-frequency/high-temperature stability.

2025–2028